Analysis apparatus and methods are essential for developing, manufacturing, inspecting, and qualifying ICs; and much time and effort is spent each year in the development of new and improved apparatus and methods for analyzing ICs. IC analysis includes the location, identification, and mapping of a portion or the entirety of an IC to reveal defects or logic states; and IC analysis may further include the control and switching of logic states in portions of the IC for purposes of analysis. The capability provided by IC analysis apparatus and methods is useful for gaining insight into design, manufacturing, and processing defects; and other device failure modes. IC analysis is the key to corrective action for improving the yield and reliability of ICs.
A problem in the development and manufacture of ICs is the detection of defects in the ICs. An example of a detect that IC analysis methods may be applied to is open-circuit electrical conductors in ICs. Open-circuit electrical conductors may be defined as an electrically conducting pathway or means whose ability to transfer electrical signals from one part of the IC to another part of the IC has been compromised by one or more failure mechanisms. Examples of mechanisms that can produce open-circuit electrical conductors include stress voiding, electromigration, silicon migration in contact metallization, and design and processing defects.
Another problem that IC analysis may be applied to is the identification and mapping of logic states in an IC. This logic state mapping or imaging is useful for examining the operation of one or more components of the IC for development or testing purposes, or as an aid in failure analysis. A third problem that IC analysis may be applied to is the control and switching of the logic state of one or more components of an IC for development or testing purposes, or as an aid in failure analysis.
The large effort devoted by the IC industry to analyzing ICs is indicative of the need for the development of new and improved apparatus and methods for analyzing ICs. As each succeeding generation of ICs becomes more complex with reduced feature sizes, reduced conductor line widths, and an increased number of interconnecting layers new and improved approaches to IC analysis are required.
A large number of different methods for IC analysis exist in the prior art as disclosed in the articles entitled, "IC Failure Analysis: Techniques and Tools for Quality and Reliability Improvement," by J. M. Soden and R. E. Anderson, Proceedings of the IEEE, Vol. 81, May 1993, pp. 703-715 and "Advanced Scanning Electron Microscopy Methods and Applications to Integrated Circuit Failure Analysis," by E. I. Cole, C. R. Bagnell Jr., B. G. Davies, A. M. Neacsu, W. V. Oxford, and R. H. Propst, Scanning Microscopy, Vol 2, No. 1, 1988, pp. 133-150.
Among the types of methods for IC failure analysis are active methods that measure the response of the IC to applied stimulus including electron, photon, or ion beams. Examples of active electron beam methods for IC failure analysis include electron beam induced current (EBIC), biased resistive contrast imaging (BRCI), and charge-induced voltage alteration (CIVA). A prior art active photon beam method for IC failure analysis is biased optical beam induced current (biased-OBIC). Logic levels of internal IC transistors have also been measured with active photon beam methods. These prior art methods for IC analysis are preferably practiced with the use of a scanning electron microscope (SEM) or a scanning optical microscope (SOM). The SEM or SOM preferably provides the capability for the simultaneous viewing of an image of the IC device structure with the active electron or photon beam excitation of the IC for analysis. The image of the IC device structure may then be combined with the analysis signal produced by the active electron or photon beam excitation to aid in registering the locations of the defects or logic states in the IC.
The EBIC method is used to identify defects in the device layer of an IC by generating an electron-hole current in semiconductor junctions in the IC. A disadvantage of the EBIC method is that for ICs, which preferably have a passivation layer, the primary electron beam must have sufficient energy to penetrate through the passivation layer to reach the semiconductor device layer in the IC. This penetration of the IC passivation layer requires a high-energy electron beam energy of up to 5,000 electron volts (eV) or more; and this high electron beam energy can result in radiation damage in metal-oxide-semiconductor (MOS) ICs.
Electron beam induced damage to MOS ICs is discussed in an article entitled "Electron Beam Induced Damage on Passivated Metal Oxide Semiconductor Devices," by S. Gorlich and E. Kubalek, Scanning Electron Microscopy, Vol. I, 1985, pp. 87-95. Electron beam induced damage to ICs is more severe for MOS ICs than for bipolar ICs due to a penetration of the primary electrons into the deep-lying gate oxide. Studies of the influence of electron irradiation not penetrating to the gate oxide on the characteristics of passivated NMOS transistors, for example, show that significant damage can occur even when the primary electrons do not penetrate to the gate oxide. This damage is due to secondary x-rays generated by the primary electrons in the passivation layer of the IC, since these x-rays penetrate into the gate oxide. The primary damage mechanism in the gate oxide is the generation of electron-hole pairs and the subsequent trapping of positive holes that then causes a change in the space charge. This change in the space charge results in a shift in the threshold voltage, V.sub.th, of the transistor. (The threshold voltage is defined as the transistor gate voltage required to generate a specified drain-to-source current at a specified drain-to-source voltage.) Furthermore, interface states at the gate oxide boundary may be affected. Both effects are responsible for altering the device parameters.
The BRCI method generates a relative resistance map of the conductors on ICs by using the IC as a complex current divider. This method for the measurement of IC logic levels and conductor voltage levels in an IC is disclosed in a paper entitled "A New Technique for Imaging the Logic State of Passivated Conductors: Biased Resistive Contrast Imaging," by E. I. Cole Jr., presented at the 1990 International Reliability Physics Symposium, New Orleans, La., Mar. 27-29, 1990. The BRCI image is generated by monitoring small fluctuations in the power supply current of an IC as an electron beam is scanned over the IC device surface. A disadvantage of the BRCI method is that the electron beam energy is comparable to that of the EBIC method and can therefore produce radiation damage in MOS ICs.
A CIVA method employing a high-energy primary electron beam for analyzing open-circuit electrical conductors in passivated ICs (i.e. ICs having one or more insulating passivation layers for forming a surface passivation device) is disclosed in a paper entitled "Rapid Localization of IC Open Conductors Using Charge-Induced Voltage Alteration," by E. I. Cole Jr. and R. E. Anderson presented at the 1992 International Reliability Physics Symposium, San Diego, Calif., Mar. 30-Apr. 2, 1992. The CIVA method provides a fast, simple method for locating open-circuit electrical conductors, contact, and via defects in ICs. The CIVA image is generated by monitoring the voltage shifts in a constant-current power supply as a high-energy (about 5,000 eV or more for a passivated IC) electron beam is scanned over a biased IC. A disadvantage of the CIVA method is that the electron beam energy is comparable to that of the EBIC and BRCI methods and can similarly produce radiation damage in MOS ICs.
Optical methods for IC analysis use a low-energy photon beam (about 2 electron volts or less) and therefore do not produce radiation damage in MOS ICs as is generally the case for high-energy electron beam methods. Optical methods for IC analysis also do not require a vacuum system or enclosure as do electron and ion beam methods. This ability to operate in the open without a vacuum system or enclosure reduces the measurement time considerably by eliminating the vacuum pump-down and return-to-atmospheric pressure times as required with electron or ion beam methods. As a result, the analysis time for optical methods may be on the order of one minute or less as compared with a minimum of several minutes for electron or ion beam methods.
The prior art biased-OBIC method for IC failure analysis is disclosed in articles entitled "Imaging Latch-Up Sites in LSI CMOS with a Laser Photoscanner," by D. J. Burns and J. M. Kendall, in Proceedings of the International Reliability Physics Symposium, 1983, pp. 118-121; "Optical Beam Induced Current Applications for Failure Analysis of VLSI Devices," by K. S. Wills, T. Lewis, G. Billus, and H. Hoang, in Proceedings of the International Symposium on Testing and Failure Analysis (ISTFA), 1990, pp. 21-26; and "Detection and Localization of Gate Oxide Shorts in MOS Transistors by Optical-Beam-Induced Current," by E. Zaroni, G. Spiazzi, G. D. Libera, B. Bonati, M. Muschitello, and C. Canali, IEEE Transactions on Electronic Devices, Vol. 38, February 1991, pp. 417-419.
The prior art biased-OBIC method is based on the use of photons to generate a photocurrent in a reverse-biased semiconductor p-n junction in an IC. The incident light is optimized for analysis by selecting a photon energy that is transparent to the passivation and underlying oxides in the IC and is absorbed by the IC substrate. The reverse-biased semiconductor p-n junction irradiated by the incident light has a photogenerated (i.e. photon generated) electrical current that is proportional to the intensity of the incident light; and this photogenerated current adds to the reverse saturation current causing the p-n junction to draw more current than under non-illuminated conditions. As the light source is scanned over the IC, the photogenerated current produces changes in the IC power supply current and this current signal provides insight into defect location. The prior art biased-OBIC method has been used to initiate latch-up conditions in complimentary metal-oxide semiconductor (CMOS) ICs to identify latch-up sensitive circuits; and it is also applicable to the detection of gate oxide short circuits and diffusion defects in ICs.
The prior art use of an active photon beam method to measure and control logic levels in transistors in an IC by the use of a visible (632.8 nm) helium-neon laser is disclosed in an article entitled "Laser Scanning of MOS IC's Reveals Internal Logic States Nondestructively," by D. E. Sawyer and D. W. Berning, Proceedings of the IEEE, Vol. 64, November 1976, pp. 393-394. The apparatus used for measuring and controlling transistor logic levels in an IC is similar to the prior-art biased-OBIC apparatus; and the information which describes the circuit operation is extracted by monitoring variations in the power supply current to the device. In this prior-art method, the laser light incident on the device surface of the IC could be used to change the internal logic states of the IC by increasing the laser intensity with a polarizer-analyzer combination in the optical system. This article makes no mention of the possibility or desirability of performing such logic level measurement or control by using an infrared laser beam transmitted through the IC substrate.
A second prior art use of an active photon beam method to measure and control logic levels in transistors in an IC is disclosed in an article entitled "Logic Failure Analysis of CMOS VLSI Using a Laser Probe," by F. J. Henley, in Proceedings of the International Reliability Physics Symposium, 1984, pp. 69-75. This second article is similar to the Sawyer et al article, except that a current-to-voltage converter (separate from the IC) is used to convert the photogenerated current signal into a voltage signal for further amplification and measurement. This second article uses a helium-neon laser incident on the device surface of the IC; and the article makes no mention of the possibility or desirability of performing such logic level measurement or control by using an infrared laser beam transmitted through the IC substrate. Blocking of the incident laser light from the device layer in the IC by the top metallization layers was known to be a problem with this prior-art method; but no solution was known or proposed other than incorporating into the IC design optical windows for nodes having 100% metal coverage (i.e. providing optical access to all the semiconductor interfaces and junctions in the IC).
The light-induced voltage alteration (LIVA) apparatus and method of the present invention is an improvement over the prior art active photon beam apparatus and methods. LIVA, in a manner similar to the prior-art active photon beam methods, uses photogenerated electron-hole pairs in a semiconductor to yield information about IC defects and functionality (i.e. logic states). When a photon beam is used to produce electron-hole pairs at or near a semiconductor interface or a semiconductor junction between regions of different doping type (e.g. a semiconductor-semiconductor interface, a semiconductor-metal interface, or a semiconductor p-n junction) in an unbiased IC, the charge carriers (electrons and holes) are separated in polarity by the built-in electrical potential between the differently doped regions that have different Fermi energy levels. For example, a CMOS transistor in the "off" state has a voltage difference (i.e. a voltage gradient) between the transistor's source and drain regions. This voltage gradient acts to separate the photogenerated electron-hole pairs to produce a photogenerated electrical current in the IC.
In the prior art biased-OBIC method and the other prior art active photon beam methods a constant-voltage power supply is used; and the photogenerated current acts to increase or decrease the current from the power supply. The small analysis current signal generated by the prior art active photon beam methods as compared to the much larger power supply bias current to the IC is disadvantageous. Furthermore, the small analysis current signal in general must be amplified in order to form an analysis image of the IC.
The LIVA analysis method of the present invention is an improvement over these prior-art methods since LIVA uses a constant-current power supply to power the IC. To maintain the voltage difference across the source and drain of a transistor in the IC supplied by the constant-current power supply, the power supply current must increase by the amount of the photogenerated current. However, since the electrical current in the constant-current supply is fixed at a constant value and cannot change in response to the photogenerated current, the power supply voltage instead increases or decreases as a result of the photogenerated current. Thus, the IC acts as its own current-to-voltage amplifier generating a large voltage change of up to several volts. The LIVA signal is this voltage change of the constant-current power supply as a light beam is scanned over a surface of the IC. In use, the LIVA signal is preferably combined with a position signal from the scanned light beam to produce a LIVA image of the IC showing the location of defects or logic states of the IC.
An advantage of the LIVA method of the present invention over the biased-OBIC and other prior art active photon beam methods is that the voltage signal generated by the LIVA method can be many orders of magnitude larger than the current signal of the prior art biased-OBIC optical method. This LIVA voltage signal may be, for example, about 2.4 volts as compared with about 80 nanoamperes current for the prior art biased-OBIC signal for a single CMOS transistor in an IC. The LIVA voltage signal is generally a sizable fraction of the operating voltage of the IC (about 5 volts).
Another advantage of the LIVA method of the present invention is that the generated voltage signal is much easier to measure than the current signal of the prior art biased-OBIC method. Voltage measurements may be made in parallel without the amplifier limitations of the current measurement. An alternating current (ac) coupled amplifier may be used with the LIVA method to overcome the dc background limitation of the prior art biased-OBIC method due to a relatively large IC bias current.
Another advantage of the LIVA method of the present invention is that it provides a high degree of selectivity for localizing and imaging defects. The LIVA method has been able to reveal defect sites in ICs that were not observable with the prior art biased-OBIC method even with current gains as large as 10.sup.10. Open circuits involving junctions can be imaged using LIVA with a selectivity and signal strength large enough to examine the entire IC die in one image.
Another advantage of the LIVA analysis method of the present invention is that it may be used with an infrared light source that may penetrate through the IC substrate to analyze an IC. This substrate surface or backside LIVA analysis is of particular advantage in ICs that are mounted in a flip-chip or substrate-up mode that restricts access to the device surface (i.e. the component surface) of the IC. This type of flip-chip mounting is becoming more prevalent for use with solder-bump technology and for the development of multi-chip modules. In addition, the use of a plurality of interconnection metallization layers obscures much of the component side of the IC and restricts the component side optical access to many of the IC components. The use of an optical method with an infrared light source having a photon energy chosen to allow a partial transmission through the IC substrate to the component side of the IC as in the present invention allows unrestricted access to the component semiconductor devices comprising the IC. This infrared light source also preferably has a photon energy sufficiently large for absorption by the component semiconductor junctions of the IC to produce a photogenerated electrical current signal in the IC for LIVA analysis.
These and other advantages of the LIVA method will become evident to those skilled in the art.